1. Field of the Invention
The invention generally relates to a semiconductor device and a manufacturing method thereof. More particularly, the invention relates to a semiconductor device with its driving capability improved by appropriately adjusting carrier mobility in a channel region of a MIS (Metal Insulator Semiconductor) transistor.
2. Background Art
One of the methods for improving driving capability of a semiconductor device such as a MIS transistor is to increase a drain current as a driving current. There are some factors that determine a drain current, and one of the factors is carrier mobility.
It has been known in the art that carrier mobility can be changed by changing a scattering probability or an effective mass of carriers, and the scattering probability or the effective mass of carriers can be changed by changing lattice spacing of atoms that form a semiconductor substrate.
Recently, stress application to a channel region has attracted attention as one of the methods for improving driving capability of a transistor. In this method, stress is applied to silicon that forms a substrate. As a result, a band structure of the substrate is changed and carrier mobility is improved. According to conventional study, it has been known in the art that applying tensile stress to a channel region in a channel length direction (a gate length direction) is effective to improve mobility of an n-channel MIS transistor (NMIS). It has also been known in the art that applying compressive stress to a channel region in a channel length direction (a gate length direction) is effective to improve mobility of a p-channel MIS transistor (PMIS).
Hereinafter, a conventional semiconductor device will be described in terms of carrier mobility in a channel region with reference to the accompanying drawings. FIG. 30 is a cross-sectional view showing the structure of a main part of a conventional semiconductor device.
As shown in FIG. 30, an NMOS (Negative-channel Metal-Oxide-Semiconductor) region 1005 including a p-type well is formed in a semiconductor substrate 1001. For example, the semiconductor substrate 1001 is formed from silicon. The NMOS region 1005 is defined by an element isolation region 1002. A gate portion 1013 is formed on the NMOS region 1005. The gate portion 1013 is formed from a gate insulating film 1011 and a gate electrode 1012, and the gate insulating film 1011 and the gate electrode 1012 are sequentially formed on the NMOS region 1005 in this order. A gate length direction is herein a <100> orientation. In the NMOS region 1005, an n-type source/drain diffusion layer 1007 is formed on both sides of the gate portion 1013. The n-type source/drain diffusion layers 1007 are impurity diffusion layers formed by implanting n-type impurity ions such as arsenic. Each n-type source/drain diffusion layer 1007 has an n-type extension diffusion layer 1006 having a relatively shallow junction depth. The n-type extension diffusion layer 1006 is formed under both side surfaces of the gate insulating film 1011 and the gate electrode 1012. A sidewall 1017 formed from an insulating film is formed on both side surfaces of the gate insulating film 1011 and the gate electrode 1012. The sidewall 1017 is formed from an I-shaped offset spacer 1014, an L-shaped oxide film 1015, and a SiN film 1016. The I-shaped offset spacer 1014 is in contact with the side surface of the gate portion 1013. The L-shaped oxide film 1015 covers the offset spacer 1014. The SiN film 1016 covers the oxide film 1015. A liner film 1030 is formed on the whole surface of the semiconductor substrate 1001 by a CVD (Chemical Vapor Deposition) method. In other words, the liner film 1030 covers the respective surfaces of the gate portion 1013, the sidewalls 1017, and the semiconductor substrate 1001. The liner film 1030 is a silicon nitride film including tensile stress (for example, see Japanese Patent Laid-Open Publication No. 2002-198368).